Averant Announces Release of Solidify 5.1.0

Averant's Solidify Sets New Standard in Verification of Digital Designs with Sequential Equivalency Checking and Automatic Testbench Synthesis

Hayward, Calif. - April 20, 2009 - Averant Inc., a leading provider of advanced verification technologies for digital designs, today announces the release of Solidify 5.1, which delivers new sequential equivalency checking (SEC) and automatic testbench synthesis. Averant is the First In Formal leader in property verification of RTL designs for digital integrated circuits.

Major improvements in Solidify 5.1 include:

"Optimizing a design for reduced power is now a basic necessity" commented Ramin Hojati, president of Averant. "Verifying the design has the same behavior after optimization requires the use of a property verification engine inside a sequential equivalence checker. Additionally, property verification is needed to prove environmental assumptions. With an integrated environment and the industry's leading and production-proven engines, the SEC capabilities in Solidify 5.1 enable users to develop golden RTL, and keep it functionally correct as RTL edits are made to improve power and performance".


Release 5.1 is available immediately, and includes sequential equivalency features in pre-release form.

About Averant

Averant Inc., founded in 1997, is a privately held EDA firm pioneering new technologies for formal verification of digital designs. Averant's flagship product is Solidify, a robust platform for property, protocol, and timing constraint verification, and for automatic design checks - all without the need for simulators or test vectors. These tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, see our web site at http://www.averant.com.

For inquiries:
Ramin Hojati
Averant, Inc.
+1-510-581-8881 x320

april 20, 2009

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