Solidify allows HDL designers to quickly and exhaustively check expected behaviors (properties) of a design. It uncovers difficult to reach corner cases and provides a guarantee that the design is correct with respect to the behaviors checked. Solidify's static coverage technology guides the designer to create a complete set of properties. Once a property set is developed, it can be easily maintained, can be quickly run, and provides an exhaustive verification of the design. Solidify is used at the block-level to ensure that blocks are clean. Using clean blocks minimizes the number of bugs found at integration, and improves the overall quality of the design.

With simulation based technologies, the designer sets up a set of testbenches, each consisting of a vector generation part and a set of self-checking tests. Additionally, the designer needs to use a coverage tool or set up coverage metrics inside the testbench to monitor the quality of the testbench as to how well it exercises the design. Testbenches take a long time to develop, are hard to maintain, take a long time to run, provide no correctness guarantees, are hard to analyze with respect to quality, and may miss difficult corner cases as they statistically cover a small portion of the state space of the design. The shortcomings will not improve much with faster simulation technologies. For example, assume the block under test has 200-inputs and 1000 flip-flops. Assume the current simulation technologies allow for simulating 230 vectors. Assume there is a simulation technology available which allows 260 vectors to be simulated over 50 cycles. The number of possible combinations of inputs over 50 cycles is 210000. The percentage of checked input sequences improves from 230/210000 to 260/210000. These numbers are practically identical as they agree in the first 3000 digits. The chance of catching a bug which could not be caught with the initial 230 vectors but can be caught with the additional ones is very small. Note that the faster simulator has not alleviated any of the other problems inherent with testbenches. Solidify's static technology allows for developing verification environments which exhaustively verify the design thus hitting difficult to reach corner cases, provides correctness guarantees, can be run quickly, and can be maintained easily.

Solidify is used by designers prior to synthesis to verify the functional behavior of their RTL blocks.

It is like a model checker in that behaviors or properties of a design are verified to comply with a specification. It is not a model checker since they are slow, capacity-limited, require special training to write properties for them, and have no interactive use model.

Averant has implemented unique new algorithms that delivers the speed & capacity improvement plus ease-of-use to make a practical analysis tool for the everyday RTL designer. This is in contrast to current tools (model checkers) that are limited to just 1-2K gates, 100-200 latches or registers, and take minutes-to-hours to run and require special training (CAD experts) to use. Solidify typically verifies a behavior in just a few seconds and runs on much larger blocks

Solidify is not an equivalence checker, which just compares two versions of the same design. Solidify?s static functional verification ensures that a designers HDL code implements its functional specification i.e. it verifies that the golden RTL is correct.

Solidify is not a simulator since it uses static approach to verification. No vectors or symbolic inputs are used or needed . Solidify instead verifies the expected behavior of a design written as properties. It can confirm, for example, that an arbiter does grant to more than one requester.

No. Solidify is a static functional analysis tool. It uses no vectors (like other static tools), but you write properties or behaviors that are verified by Solidify.

Solidify is surprisingly quick and easy to learn. The Integrated Design Environment (IDE) is intuitive, and Averant?s hardware property language (HPL) is simple and regular . A one-day training course is offered to new users, but many have picked it up on their own in a few days.

Yes. Solidify can correctly verify systems with multiple clocks that run at different frequencies. It will verify, for example, that a data transfer based on two different clocks will occur correctly without specifying the timing relationship of the two clocks. An explanation of multiple clocks is given in the Solidify Users Guide.

Solidify is supported on workstations and personal computers running Microsoft Windows NT, Windows 2000, Sun Solaris, Linux, and HP-UX operating systems.

Solidify is licensed using the FLEXlm license manager software from Globetrotter. Solidify licenses are floating and can move to any workstation on a network.

Solidify supports both black-box and white-box testing. Properties can be written with respect to just the inputs and outputs for a particular block or unit. This may not provide complete coverage of the blocks HDL, which can be determined by Solidify?s Coverage Analysis. White-box testing then would be used.

Solidify complements your existing synthesis design flow. Instead of using simulation both at the block-level and the chip-level, Solidify lets you replace simulation for block-level verification, leaving simulation or emulation for chip-level verification.

No modifications in your HDL are needed to use Solidify.

Yes. Either VHDL or Verilog can be used with Solidify.

Solidify is targeted to the day-to-day HDL designer who need a fast tool that can kill bugs with less effort than simulation.

For block-level verification, Solidify can replace simulation, since it has the speed, capacity and ease-of-use to find bugs in your HDL.

bus arbiters

cache controllers


arithmetic blocks

data paths


reset circuitry

bus interfaces


instruction and address decoders


transaction protocols

state machines

The coverage option to Solidify provides design coverage analysis to assure that all portions of a block have been verified for some behavior. If some portion of a block does not have a property covering its logic then Solidify reports it as uncovered and should be attended to by the designer. Advanced algorithms eliminate false coverage problems seen in traditional code coverage tools. Solidify?s coverage analysis has no impact on verification times since it i s a separate step. Incremental coverage analysis is supported so the designer saves time and effort since only those unverified portions of the circuit are analyzed.

Lint checkers are tools which can check some problems of a design just on the basis of analyzing the code. Lint checkers are useful, but they are very limited and do not replace property checking which verifies the functional behavior. We think a good verification methodology at the block-level should be running some fast lint checks, and then a good property set. A property set catches many problems which are impossible for a lint tool. For example, if you change an AND gate in your design to an OR gate, no lint checking program will flag this. Since the behavior most likely has changed, a good property set would catch the change. Solidify helps the user build a good property set via its coverage technology. In summary, lint checks are useful, but property ch ecking is indispensable.