Oakland, Calif. - Aug. 31, 2016 - Averant Inc., the First In Formal^TM leader in property verification of RTL designs for digital circuits, today announced the release of Solidify 6.3. Some of the highlights of this release are listed below.

• Assumption Consistency Checker. Assumptions are an integral part of block level verification. Solidify 6.3 adds a tool which flags internal inconsistencies in the assumption set.
• Improved Hierarchical Verification. Hierarchical verification improves performance of property verification by proving properties at the lowest possible level. Solidify 6.3 further improves the efficiency of this process for properties which need to be automatically promoted to higher levels for verification.
• Improved Property Coverage. Averant's patented property coverage guides the user in areas where additional properties are needed. In release 6.3, Solidify's autoverify and coverage have been integrated allowing for coverage to use results of autoverify.

Release 6.3 also contains improved property debugging, improved System Verilog support, and more control over property selection as well as bug fixes.

"Averant has been pushing the frontiers of property verification for many years now" commented Ramin Hojati, president of Averant. "Release 6.3 brings additional features which improve usability and performance of Solidify".

Availability

Release 6.3 is available for use immediately.

About Averant

Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant's signature product is Solidify, a robust platform for property, protocol, and automatic design checks - all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.

For inquiries:

Ramin Hojati
Averant, Inc.
rhojati@averant.com

Aug 17, 2021


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