Oakland, Calif. - Nov. 21, 2016 - Averant Inc., the First In Formal^TM leader in property verification of RTL designs for digital circuits, today announces the release of an extensive video tutorial library, which complements its on-site training, consulting and support services. A sample number of these videos has been released in public domain. These videos cover various features of Solidify such as property verification, System Verilog Assertions, sequential equivalency checking, gate level support, bug hunting, various engines, modeling, autochecks, coverage , multiple clock support and TCL interface.

"Solidify is a feature rich state of the art formal verification tool, embodying important contributions to computer science, and requiring training to best utilize" commented Ramin Hojati, president of Averant. "While we think an initial on-site training is an excellent way to get started, these videos should help users sharpen their skills as they attack new problems utilizing Solidify".

Availability

These training videos are available immediately.

About Averant

Averant Inc. is a privately held EDA firm specializing in formal verification of digital designs. Averant's signature product is Solidify, a robust platform for property, protocol, and automatic design checks - all without the need for simulators or test vectors. Averant's tools are easily adopted into the design flow, and help improve quality, reduce risk, and speed the design process. For more information, visit http://www.averant.com.

For inquiries:

Ramin Hojati
Averant, Inc.
rhojati@averant.com

Aug 17, 2021


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