SolidifyTM
Unrivaled property verification. A high performance static functional verifier, Solidify stands as the most technologically advanced tool in its class. Provided as complete property verification environment, it includes multi-language support, source code debugging, interfaces to simulation, plus a host of advanced features.
Painstakingly enhanced and refined during its over 10 years in production, Solidify is a mature and widely deployed tool. Boasting both speed and capacity, it represents the state of the art in property verification.
Peerless and powerful, Solidify is the tool to beat.
Functionality
- Property verification, Multiple formal engines, Sequential redundancy removal, Testbenchless bug hunting, Source-code debugging
- Customizable engine cooordination, Patented Property code coverage, Reset sequence guessing
- Hierarchical verification, Multiple clock support, Memory model generation, Multi threading, Verification database, Poperty lint, Pass property trace, and more
- Verilog, VHDL, SystemVerilog, mixed
- SVA, PSL, OVA, OVL, HPL property languages
- VCD, SDC, LIB
- Property Analysis, Debug Tracing, Wave forms
- Testbench generation, Synthesizable monitor generation, Property languages cross translation
- Coverage Reporting
A First Demo of Hardware Property Verification
SVA: Essentials for Formal Verification