Bringing verification closure to power reduction flows and other sequential optimizations
SolidSEC is a powerful Sequential Equivalency Checker (SEC) built on Averant's formal verification technology. It contains a state of the art Combinational Equivalency Checker (CEC) accepting both RT and gate level designs. Developed over many years of research and collaboration with industrial and educational partners, it easily integrates into power reduction flows, as well as other sequential optimizations, bringing the strength of formal verification to such designs. With increasingly sophisticated power saving design techniques becoming commonplace, integration of SolidSEC is an indispensable step to guarantee the overall design correctness.
Sequential redundancy removal to improve verification performance
Modern designs contain redundant logic, which can impede verification performance. SolidSEC integrates seemlessly into Solidify, with 2 simple commands, to remove redundancies and improve verification performance. Powerful sequential redundancy removal is a must in any modern and complete property verification tool.